Conventional binary-search analog-to-digital converters use an algorithm to gradually bring a reference signal of a comparator closer to an input analog signal by comparison based on a binary search in a similar manner to SAR analog-to-digital converters. Fewer comparators are operated therein as compared to flash analog-to-digital converters in which comparators of the same number as the desired number of bits and having different reference signals from each other are connected in parallel to each other and all the comparators are operated in a single comparison operation. Thus, power consumption can be reduced.
In a similar manner to the flash analog-to-digital converters, in the binary-search analog-to-digital converters, comparators of the same number as the desired number of bits and having constant reference voltages are prepared in advance. Based on a comparison result of a higher bit, a comparator having a reference signal close to an input signal for use in comparison of the next bit is selected. Since the reference voltage of each comparator has a constant value before being selected, a time for regulating a threshold voltage by feeding back the comparison result of the higher bit is not required. Thus, the binary-search analog-to-digital converters can be operated at higher speed than the SAR analog-to-digital converters.
In the conventional binary-search analog-to-digital converters, analog signal input terminals of all the comparators are short-circuited.
A buffer circuit such as a source-follower circuit and a sample-hold circuit is normally added to a position frontward of an analog-to-digital converter to ensure resolution. By adding the buffer circuit, an output impedance is reduced to a desired value. The accuracy of an analog signal input into a comparator can be thereby maintained within a desired signal band.
Generally, when the output load capacitance of the buffer circuit increases, the output impedance of the buffer circuit needs to be reduced corresponding thereto. The buffer circuit thereby consumes more power. In the aforementioned conventional technique, the analog signal input terminals of the comparators of the same number as that in the flash analog-to-digital converter are short-circuited. Thus, when the number of bits of the analog-to-digital converter is increased, the number of comparators is also exponentially increased. Along with the increase in the number of comparators, the parasitic capacitance of the analog signal input terminals increases. A wiring for short-circuiting the comparators is also extended, so that the wiring parasitic capacitance also increases. There is a disadvantage that the buffer circuit consumes more power as the parasitic capacitance increases.
As described above, the conventional binary-search analog-to-digital converters have a problem that when the number of comparators is increased to increase the number of bits, the parasitic capacitance of the analog signal input terminals becomes larger, so that the buffer circuit connected to a position frontward thereof consumes more power.